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XC95288XV High-Performance CPLD
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DS050 (v3.0) June 25, 2007
Product Specification
Note: This product is being discontinued. You cannot order parts after May 14, 2008. Xilinx recommends replacing XC95288XV devices with equivalent XC95288XL devices in all designs as soon as possible. Recommended replacements are pin compatible, however require a VCC change to 3.3V, and a recompile of the design file. In addition, there is no 1.8V I/O support, and only one output bank is supported. See XCN07010 for details regarding this discontinuation, including device replacement recomendations for the XC95288XV CPLD.
Power Estimation
Power dissipation in CPLDs can vary substantially depending on the system frequency, design application and output loading. To help reduce power dissipation, each macrocell in a XC9500XV device may be configured for low-power mode (from the default high-performance mode). In addition, unused product-terms and macrocells are automatically deactivated by the software to further conserve power. For a general estimate of ICC, the following equation may be used: PTOTAL = PINT + PIO = ICCINT x VCCINT + PIO Separating internal and I/O power here is convenient because XC9500XV CPLDs also separate the corresponding power pins. PIO is a strong function of the load capacitance driven, so it is handled by I = CVf. ICCINT is another situation that reflects the actual design considered and the internal switching speeds. An estimation expression for ICCINT (taken from simulation) is: ICCINT(mA) = MCHS(0.122 X PTHS + 0.238) + MCLP(0.042 x PTLP + 0.171) + 0.04(MCHS + MCLP) x fMAX x MCTOG where: MCHS = # macrocells used in high speed mode MCLP = #macrocells used in low power mode PTHS = average p-terms used per high speed macrocell PTLP = average p-terms used over low power macrocell fMAX = max clocking frequency in the device MCTOG = % macrocells toggling on each clock (12% is frequently a good estimate This calculation was derived from laboratory measurements of an XC9500XV part filled with 16-bit counters and allowing a single output (the LSB) to be enabled. The actual ICC value varies with the design application and should be verified during normal system operation. Figure 1 shows the above estimation in a graphical form. For a more detailed discussion of power consumption in this device, see Xilinx
Features
* * 288 macrocells with 6,400 usable gates Available in small footprint packages - 144-pin TQFP (117 user I/O pins) - 208-pin PQFP (168 user I/O pins) - 280-pin CSP (192 user I/O pins) - 256-pin FBGA (192 user I/O pins) Optimized for high-performance 2.5V systems - Low power operation - Multi-voltage operation Advanced system features - In-system programmable - Four separate output banks - Superior pin-locking and routability with Fast CONNECTTM II switch matrix - Extra wide 54-input Function Blocks - Up to 90 product-terms per macrocell with individual product-term allocation - Local clock inversion with three global and one product-term clocks - Individual output enable per output pin - Input hysteresis on all user and boundary-scan pin inputs - Bus-hold ciruitry on all user pin inputs - Full IEEE Standard 1149.1 boundary-scan (JTAG) Fast concurrent programming Slew rate control on individual outputs Enhanced data security features Excellent quality and reliability - 20 year data retention - ESD protection exceeding 2,000V
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Description
The XC95288XV is a 2.5V CPLD targeted for high-performance, low-voltage applications in leading-edge communications and computing systems. It is comprised of 16 54V18 Function Blocks, providing 6,400 usable gates with propagation delays of 6 ns.
(c) 2005, 2007 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS050 (v3.0) June 25, 2007 Product Specification
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XC95288XV High-Performance CPLD application note XAPP361, "Planning for High Speed XC9500XV Designs."
450 400 350
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Typical I CC (mA)
300 250 200 150 100 50 0 50
Hig
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an
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w Lo
Po
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100
150
200
250
Clock F requency (MHz)
DS050_01_041405
Figure 1: Typical ICC vs. Frequency for XC95288XV
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XC95288XV High-Performance CPLD
3 JTAG Port 1
JTAG Controller
In-System Programming Controller
54 I/O I/O I/O 18
Function Block 1 Macrocells 1 to 18
Fast CONNECT II Switch Matrix
I/O
54 18
Function Block 2 Macrocells 1 to 18
I/O Blocks I/O I/O I/O I/O 3 I/O/GCK 1 I/O/GSR 4 I/O/GTS
54 18
Function Block 3 Macrocells 1 to 18
54 18
Function Block 4 Macrocells 1 to 18
54 18
Function Block 16 Macrocells 1 to 18
DS055_02_101300
Figure 2: XC95288XV Architecture (Function Block outputs (indicated by the bold line) drive the I/O Blocks directly.)
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Supported I/O Standards
Table 1: IOSTANDARD Options IOSTANDARD LVTTL LVCMOS2 X25TO18 VCCIO 3.3V 2.5V 1.8V
The LVTTL I/O standard is a general purpose EIA/JEDEC standard for 3.3V applications that use an LVTTL input buffer and Push-Pull output buffer. The LVCMOS2 standard is used in 2.5V applications. XC9500XV CPLDs are also 1.8V I/O compatible. The X25TO18 setting is provided for generating 1.8V compatible outputs from a CPLD normally operating in a 2.5V environment. The ISE software automatically groups outputs with matching IOSTANDARD settings into the same VCCIO bank when no location constraints are specified. The default I/O Standard for pads without IOSTANDARD attributes is LVTTL for XC9500XV devices.
The XC95288XV CPLD features both LVCMOS and LVTTL I/O implementations. See Table 1 for I/O standard voltages.
Absolute Maximum Ratings
Symbol VCC VCCIO VIN VTS TSTG TJ Description Supply voltage relative to GND Supply voltage for output drivers Input voltage relative to GND(1) Voltage applied to 3-state output(1) Storage temperature (ambient) Junction temperature Value -0.5 to 2.7 -0.5 to 3.6 -0.5 to 3.6 -0.5 to 3.6 -65 to +150 +150 Units V V V V
oC oC
Notes: 1. Maximum DC undershoot below GND must be limited to either 0.5V or 10 mA, whichever is easier to achieve. During transitions, the device pins may undershoot to -2.0V or overshoot to +3.6V, provided this over- or undershoot lasts less than 10 ns and with the forcing current being limited to 200 mA. 2. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability. 3. For solder specifications, see Xilinx Packaging.
Recommended Operation Conditions
Symbol VCCINT VCCIO Parameter Supply voltage for internal logic and input buffers Commercial TA = 0oC to +70oC Min 2.37 2.37 3.0 2.37 1.71 0 1.7 0 Max 2.62 2.62 3.6 2.62 1.89 0.8 3.6 VCCIO V V V V V V Units V
Industrial TA = -40oC to +85oC
Supply voltage for output drivers for 3.3V operation Supply voltage for output drivers for 2.5V operation Supply voltage for output drivers for 1.8V operation
VIL VIH VO
Low-level input voltage High-level input voltage Output voltage
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Quality and Reliability Characteristics
Symbol TDR NPE VESD Data retention Program/Erase cycles (endurance) Electrostatic Discharge (ESD) Parameter Min 20 1,000 2,000 Max Units Years Cycles Volts
DC Characteristics Over Recommended Operating Conditions
Symbol VOH Parameter Output high voltage for 3.3V outputs Output high voltage for 2.5V outputs Output high voltage for 1.8V outputs VOL Output low voltage for 3.3V outputs Output low voltage for 2.5V outputs Output low voltage for 1.8V outputs IIL Input leakage current Test Conditions IOH = -4.0 mA IOH = -1.0 mA IOH = -100 A IOL = 8.0 mA IOL = 1.0 mA IOL = 100 A VCC = 2.62V VCCIO = 3.6V VIN = GND or 3.6V VCC = 2.62V VCCIO = 3.6V VIN = GND or 3.6V VCC min < VIN < 3.6V CIN ICC I/O capacitance Operating supply current (low power mode, active) VIN = GND f = 1.0 MHz VI = GND, No load f = 1.0 MHz Min 2.4 2.0 90% VCCIO Max 0.4 0.4 0.4 10 Units V V V V V V A
IIH
Input high-Z leakage current
-
10
A
59
150 10
A pF mA
AC Characteristics
XC95288XV-6 Symbol TPD TSU TH TCO fSYSTEM TPSU TPH TPCO TOE TOD TPOE TPOD Parameter I/O to output valid I/O setup time before GCK I/O hold time after GCK GCK to output valid Multiple FB internal operating frequency I/O setup time before p-term clock input I/O hold time after p-term clock input P-term clock output valid GTS to output valid GTS to output disable Product term OE to output enabled Product term OE to output disabled Min 4.0 0 1.0 2.6 Max 6.0 3.8 208 6.8 4.5 4.5 8.4 8.4 XC95288XV-7 Min 4.8 0 1.6 3.2 Max 7.5 4.5 125.0 7.7 5.0 5.0 9.5 9.5 XC95288XV-10 Min 6.5 0 2.1 4.4 Max 10 5.8 100.0 10.2 7.0 7.0 11.0 11.0 Units ns ns ns ns MHz ns ns ns ns ns ns ns
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XC95288XV High-Performance CPLD
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XC95288XV-6 Symbol TAO TPAO TWLH TPLH TAPRPW Parameter GSR to output valid P-term S/R to output valid GCK pulse width (High or Low) P-term clock pulse width (High or Low) Asynchronous preset/reset pulse width (High or Low) Min 2.4 6.0 6.0 Max 10.8 11.8 -
XC95288XV-7 Min 4.0 6.5 6.5 Max 12.0 12.6 -
XC95288XV-10 Min 5.0 7.0 7.0 Max 14.5 15.3 Units ns ns ns ns ns
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VTEST R1 Device Output R2 CL
Output Type
VCCIO 3.3V 2.5V 1.8V
VTEST 3.3V 2.5V 1.8V
R1 320 250 10K
R2 360 660 14K
CL 35 pF 35 pF 35 pF
DS050_03_110101
Figure 3: AC Load Circuit
Internal Timing Parameters
XC95288XV-6 Symbol Buffer Delays TIN TGCK TGSR TGTS TOUT TEN TPTCK TPTSR TPTTS TPDI TSUI THI TECSU TECHO TCOI TAOI TRAI TLOGI TLOGILP TF TPTA TPTA2 TSLEW Input buffer delay GCK buffer delay GSR buffer delay GTS buffer delay Output buffer delay Output buffer enable/disable delay Product term clock delay Product term set/reset delay Product term 3-state delay Combinatorial logic propagation delay Register setup time Register hold time Register clock enable setup time Register clock enable hold time Register clock to output valid time Register async. S/R to output delay Register async. S/R recover before clock Internal logic delay Internal low power logic delay Fast CONNECT II feedback delay Incremental product term allocator delay Adjacent macrocell p-term allocator delay Slew-rate limited delay 2.0 1.6 2.0 1.6 6.0 2.2 1.2 2.2 4.5 2.4 0 2.0 1.0 6.2 0.4 0.2 6.2 1.0 5.5 1.6 0.8 0.3 3.5 2.6 2.2 2.6 2.2 7.5 1.4 6.4 3.5 0.8 0.3 4.0 2.3 1.5 3.1 5.0 2.5 0 2.4 1.4 7.2 1.3 0.5 6.4 3.0 3.5 3.0 3.5 10.0 3.5 1.8 4.5 7.0 3.0 0 2.7 1.8 7.5 1.7 1.0 7.0 1.8 7.3 4.2 1.0 0.4 4.5 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Parameter Min Max XC95288XV-7 Min Max XC95288XV-10 Min Max Units
Product Term Control Delays
Internal Register and Combinatorial Delays
Feedback Delays Time Adders
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XC95288XV I/O Pins
Function Block Macrocell TQ144 PQ208 FG256 CS280 BScan Order Bank Function Block Macrocell TQ144 PQ208 FG256 CS280 BScan Order Bank
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
20 21 22 23 24 25 26 27 9 10 11 12 13 14 15 16 17 19 -
28 29 30 31 32 33 34 35 36 37 15 16 17 18 19 20 21 22 23 25 -
H1 H5 J1 J5 J2 J3 K1 J4 K2 K5 L1 K3 D1 G4 E1 G3 G2 F5 F1 G5 H2 H4 G1 H3 -
K2 K3 K4 L1 L2 L3 L4 M1 M2 M3 M4 N1 G3 G2 G1 G4 H1 H3 H2 H4 J1 J2 J3 J4 -
861 858 855 852 849 846 843 840 837 834 831 828 825 822 819 816 813 810 807 804 801 798 795 792 789 786 783 780 777 774 771 768 765 762 759 756
1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 -
3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
28 30(1) 31 32(1) 33 2(1) 3(1) 4 5(1) 6(1) 7 -
38 39 40 41 43 44(1) 45 46(1) 47 48 3(1) 4 5(1) 6 7(1) 8 9(1) 10 12 14 -
L2 L5 M1 L4 N1 L3 M2(1) M4 P1 M3(1) N2 N4 D3(1) D2 E3(1) C2 D4(1) B1 E4 C1 E5(1) E2 F2 E6 -
N2 P1 P2 P3 P4 R1 R3(1) R2 R4 T1(1) T2 T3 C2(1) B1 C1(1) D4 D3(1) D2 D1 E3 E2(1) E4 F3 F4 -
753 750 747 744 741 738 735 732 729 726 723 720 717 714 711 708 705 702 699 696 693 690 687 684 681 678 675 672 669 666 663 660 657 654 651 648
1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 -
Notes: 1. Global control pin
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XC95288XV I/O Pins (continued)
Function MacroBlock cell TQ144 PQ208 FG256 CS280 BScan Order Bank Function Block Macrocell TQ144 PQ208 FG256 CS280 BScan Order Bank
5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
34 35 38(1) 39 40 41 43 44 135 136 137 138 139 140 142 143(1) -
49 50 51 54 55(1) 56 57 58 60 61 197 198 199 200 201 202 203 205 206(1) 208 -
R1 N3 P2 P4 P5(1) T2 N5 R4 M5 R5 R6 N6 A5 D6 B5 C6 A4 E7 A3 C5 A2 B4 C4(1) B3 -
U1 V1 U2 V3 W2(1) W3 T4 U4 V4 W4 V5 T5 D7 A6 B6 C6 D6 A5 C5 B5 D5 B4 C4(1) A3 -
645 642 639 636 633 630 627 624 621 618 615 612 609 606 603 600 597 594 591 588 585 582 579 576 573 570 567 564 561 558 555 552 549 546 543 540
1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 -
7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
45 46 48 49 130 131 132 133 134 -
62 63 64 66 67 69 70 71 72 73 186 187 188 189 191 192 193 194 195 196 -
R3 M6 T3 T4 P7 T5 N7 R7 M7 T6 N8 T7 E11 A8 C8 B8 D8 A7 E9 B7 D7 A6 B6 E8 -
W5 U6 V6 W6 U7 V7 W7 T7 W8 U8 V8 T8 B10 C10 D10 A9 B9 C9 D9 A8 B8 C8 B7 C7 -
537 534 531 528 525 522 519 516 513 510 507 504 501 498 495 492 489 486 483 480 477 474 471 468 465 462 459 456 453 450 447 444 441 438 435 432
1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 -
Notes: 1. Global control pin
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XC95288XV I/O Pins (continued)
BScan Function MacroTQ144 PQ208 FG256 CS280 Order Block cell Bank BScan Function MacroTQ144 PQ208 FG256 CS280 Order Block cell Bank
9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
50 51 52 53 54 56 57 58 59 117 118 119 120 121 124 125 126 128 129 -
74 75 76 77 78 80 82 83 84 85 86 170 171 173 174 175 178 179 180 182 183 185 -
R8 P8 T8 M8 T9 P9 R9 M9 T10 M10 R10 T11 B11 D11 A11 D10 B10 E12 F12 B9 C9 A9 D9 E10 -
U9 T9 W10 V10 U10 W11 V11 U11 T11 W12 V12 T12 C14 B14 A14 C13 B13 A13 A12 C12 B12 B11 C11 A10 -
429 426 423 420 417 414 411 408 405 402 399 396 393 390 387 384 381 378 375 372 369 366 363 360 357 354 351 348 345 342 339 336 333 330 327 324
3 3 3 3 3 3 3 3 3 3 3 3 4 4 4 4 4 4 4 4 4 4 4 4 -
11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
60 61 64 66 68 69 70 110 111 112 113 115 116 -
87 88 89 90 91 95 97 99 100 101 102 158 159 160 161 162 164 165 166 167 168 169 -
P10 T12 N10 T13 M11 N11 T14 R12 T15 R14 N13 R13 B13 B14 C13 A15 C12 B12 D13 A14 E13 A13 C11 A12 -
W13 V13 U13 T13 W14 T14 W15 V15 W16 U16 W17 W18 B19 B18 B17 A18 A17 D16 C16 B16 A16 C15 B15 D15 -
321 318 315 312 309 306 303 300 297 294 291 288 285 282 279 276 273 270 267 264 261 258 255 252 249 246 243 240 237 234 231 228 225 222 219 216
3 3 3 3 3 3 3 3 3 3 3 3 4 4 4 4 4 4 4 4 4 4 4 4 -
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XC95288XV High-Performance CPLD
XC95288XV I/O Pins (continued)
Function Block Macrocell TQ144 PQ208 FG256 CS280 BScan Order Bank Function MacroTQ144 PQ208 FG256 Block cell CS280 BScan Order Bank
13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
71 74 75 76 77 78 100 101 102 103 104 105 106 107 -
103 106 107 109 110 111 112 113 114 115 116 144 145 146 147 148 149 150 151 152 154 155 -
P13 P15 N14 R16 N15 M15 M13 P16 N16 M14 L15 L13 F15 E15 F13 D16 F14 C16 E14 D15 G12 C15 D14 B16 -
V17 U18 V19 U19 T16 T17 T18 T19 R18 R16 R19 P17 G19 G16 F19 F18 F17 F16 E19 E17 E18 E16 D18 D17 -
213 210 207 204 201 198 195 192 189 186 183 180 177 174 171 168 165 162 159 156 153 150 147 144 141 138 135 132 129 126 123 120 117 114 111 108
3 3 3 3 3 3 3 3 3 3 3 3 4 4 4 4 4 4 4 4 4 4 4 4 -
15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
79 80 81 82 83 85 86 87 88 91 92 93 94 95 96 97 98 -
117 118 119 120 121 122 123 125 126 127 128 131 133 134 135 136 137 138 139 140 142 143 -
M12 M16 K14 L16 K13 K15 L12 K16 J14 J15 J13 J16 K12 J12 H15 H14 G16 H13 G15 H16 F16 H12 E16 G14 -
P16 P19 N17 N18 N19 N16 M19 M17 M16 L19 L18 L17 L16 K18 K17 K16 J19 J18 J17 J16 H19 H18 H17 H16 -
105 102 99 96 93 90 87 84 81 78 75 72 69 66 63 60 57 54 51 48 45 42 39 36 33 30 27 24 21 18 15 12 9 6 3 0
3 3 3 3 3 3 3 3 3 3 3 3 4 4 4 4 4 4 4 4 4 4 4 4 -
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XC95288XV Global, JTAG and Power Pins
Pin Type I/O/GCK1 I/O/GCK2 I/O/GCK3 I/O/GTS1 I/O/GTS2 I/O/GTS3 I/O/GTS4 I/O/GSR TCK TDI TDO(1) TMS VCCINT 2.5V TQ144 30 32 38 5 6 2 3 143 67 63 122 65 8, 42, 84, 141 PQ208 44 46 55 7 9 3 5 206 98 94 176 96 11, 59, 124, 153, 204 FG256 M2 M3 P5 D4 E5 D3 E3 C4 P12 R11 A10 N12 F4, G6, H6, J6, K6, F7, L7, F8., L8, F9, L9, F10, L10, G11, H11, J11, K11 K4, L6, P6 C7, D5, F3, F6 L11, L14, N9, P11 C10, F11, D12, G13 A1, T1, B2, R2, C3, P3, G7, H7, J7, K7, G8, H8, J8, K8, G9, H9, J9, K9, G10, H10, J10, K10, C14, P14, B15, R15, A16, T16 CS280 R3 T1 W2 D3 E2 C2 C1 C4 T15 U14 D13 U15 E1, F2, N3, U5, W9, V9, U12, V16, R17, M18, G18, D19, C18, A15, A11, D8, A4 N4, V2, T6 A7, C3, F1, K1 T10, V14, V18, P18 K19, G17, C19, D14, D12, D11 E5, F5, G5, H5, J5, K5, L5, M5, N5, P5, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15, P15, N15, M15, L15, K15, J15, H15, G15, F15, E15, E14, E13, E12, E11, E10, E9, E8, E7, E6 A1, W1, U3, W19, U17, A19, C17, A2, B3, B2
VCCIO1 VCCIO2 VCCIO3 VCCIO4 GND
37 1 55, 73 109, 127 18, 29, 36, 47, 62, 72, 89, 90, 99, 108, 114, 123, 144
53, 65 1, 26 79, 92, 105 132, 157, 172, 181, 184 2, 13, 24, 27, 42, 52, 68, 81, 93, 104, 108, 129, 130, 141, 156, 163, 177, 190, 207
No Connects
-
-
-
Notes: 1. TDO voltage is controlled by VCCIO4.
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XC95288XV High-Performance CPLD
Device Part Marking and Ordering Combination Information
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Device Type Package Speed Operating Range
XC95xxxXV TQ144 7C
This line not related to device part number
1
Sample package with part marking.
Device Ordering and Part Marking Number XC95288XV-6TQ144C XC95288XV-6PQ208C XC95288XV-6FG256C XC95288XV-6CS280C XC95288XV-7TQ144C XC95288XV-7PQ208C XC95288XV-7FG256C XC95288XV-7CS280C XC95288XV-7TQ144I XC95288XV-7PQ208I XC95288XV-7FG256I XC95288XV-7CS280I XC95288XV-10TQ144C XC95288XV-10PQ208C XC95288XV-10FG256C XC95288XV-10CS280C XC95288XV-10TQ144I XC95288XV-10PQ208I XC95288XV-10FG256I XC95288XV-10CS280I
Speed (pin-to-pin delay) 6 ns 6 ns 6 ns 6 ns 7.5 ns 7.5 ns 7.5 ns 7.5 ns 7.5 ns 7.5 ns 7.5 ns 7.5 ns 10 ns 10 ns 10 ns 10 ns 10 ns 10 ns 10 ns 10 ns
Pkg. Symbol TQ144 PQ208 FG256 CS280 TQ144 PQ208 FG256 CS280 TQ144 PQ208 FG256 CS280 TQ144 PQ208 FG256 CS280 TQ144 PQ208 FG256 CS280
No. of Pins 144-pin 208-pin 256-ball 280-ball 144-pin 208-pin 256-ball 280-pin 144-pin 208-pin 256-ball 280-pin 144-pin 208-pin 256-ball 280-ball 144-pin 208-pin 256-ball 280-ball
Package Type Thin Quad Flat Pack Plastic Quad Flat Package Plastic Fineline Ball Grid Array Chipscale Package Thin Quad Flat Pack Plastic Quad Flat Package Plastic Fineline Ball Grid Array Chipscale Package Thin Quad Flat Pack Plastic Quad Flat Package Plastic Fineline Ball Grid Array Chipscale Package Thin Quad Flat Pack Plastic Quad Flat Package Plastic Fineline Ball Grid Array Chipscale Package Thin Quad Flat Pack Plastic Quad Flat Package Plastic Fineline Ball Grid Array Chipscale Package
Operating Range(1) C C C C C C C C I I I I C C C C I I I I
Notes: 1. C = Commercial: TA = 0 to +70C; I = Industrial: TA = -40 to +85C 2. Some packages available in Pb-free option. See Xilinx Packaging for more information.
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Revision History
Date 09/28/98 12/10/98 2/5/99 6/7/99 4/11/00 01/29/01 05/15/01 08/27/01 06/24/02 Version 1.0 1.1 1.2 1.3 1.4 2.0 2.1 2.2 2.3 Original creation of data sheet. Revision of tables. Updated pinouts to reflect BG256 (replaces BG352). Add -7 speed and CS280 package. Updated AC specifications, added bank information to pinout tables. Added -5 performance specification, deleted -6; changed BG256 package to FG256 package. Updated ICC vs. Frequency Figure 1. Updated ICC formula, Recommended Operation Conditions, -5 AC Characteristics and Internal Timing Parameters Changed VCCIO 3.3V from 3.13 to 3.0 (min), 3.46 to 3.60 (max); DC characteristics: IIL - added "low" current, IIH - changed to "Input leakage high current"; Internal Timing: -5 TAOI from 6.5 to 5.9. Updated ICC equation on page 1. Updated Figure 3: AC Load Circuit 1.8V parameters. Added second test condition and max measurement to IIH DC Characteristics. Added Part Marking Information to Ordering Information. Changed to Preliminary. Changed -5 speed to -6 speed; added -7 Industrial. Updated TSOL from 260 to 220oC. Updated Device Part Marking. Updated Package Device Marking Pin 1 orientation. Added TAPRPW specification to AC Characteristics. Added IOSTANDARD information. Notice of discontinuance. Revision
05/27/03 08/21/03 04/15/05 06/25/07
2.4 2.5 2.6 3.0
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DS050 (v3.0) June 25, 2007 Product Specification

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